1. Field of the Invention
The present invention relates to a static type semiconductor memory device, and more particularly to a semiconductor memory device in which a part of a word line and a part of a bit line can be selected at the same time in order to decrease the power consumption of the semiconductor memory device.
2. Description of the Prior Art
In recent years, the memory capacity of a semiconductor memory device has become larger and larger. When the memory capacity of a static type semiconductor memory device becomes large, a load current of each bit line becomes large and the stray capacitance of each bit line increases, so that the operating speed of the memory device becomes slow.
FIG. 1A is a schematic block diagram of a conventional static type RAM device and FIG. 1B is a partial circuit diagram of the RAM device. In these drawings, MCA designates a memory cell array having static type memory cells MC.sub.0,0 ; . . . ; MC.sub.N-1,0 ; . . . which are disposed in a matrix of N rows and M columns. For example, when a word line X.sub.0 is selected by a word address decoder WD and a bit line or bit line pair Y.sub.0 and Y.sub.0 is selected by a column decoder CD, a memory cell MC.sub.0,0 disposed on a cross point of the word line X.sub.0 and the bit line Y.sub.0 is selected. Each of the memory cells, for example MC.sub.0,0, comprises MIS transistors Q.sub.3 through Q.sub.6 and load resistors R.sub.1 and R.sub.2. Only one of the cross coupled transistors Q.sub.5 and Q.sub.6 is turned on by this means, and the other is turned off according to the information stored in the memory cell MC.sub. 0,0. When the word line X.sub.0 is selected and the potential of the word line X.sub.0 becomes, for example, high, the transfer transistors Q.sub.3 and Q.sub.4 are turned on. If the transistor Q.sub.5 is turned on, a current flows from a voltage source V.sub.DD through an MIS bit line load transistor Q.sub.1 of the bit line Y.sub.0, the transistor Q.sub.3 and the transistor Q.sub.5 to another voltage source V.sub.SS. In this condition, the transistor Q.sub.6 is turned off and no current flows through an MIS load transistor Q.sub.2 of the bit line Y.sub.0. Accordingly, there exists a potential difference between the bit lines Y.sub.0 and Y.sub.0. A sense amplifier, which is not shown in the drawings, detects the potential difference and outputs the information stored in the memory cell MC.sub.0,0. In FIG. 1B, MIS transistors Q.sub.7 and Q.sub.8 of the column decoder CD connect the selected bit line pair Y.sub.0 and Y.sub.0 to the sense amplifier under the control of the output signal from a NOR gate "NOR" which receives column address signals AC.sub.0 through AC.sub.m-1, where 2.sup.m+1 =M.
Concerning the power consumption of the above-mentioned static type RAM device, more than 60% of the total power consumption is consumed by the memory cell array portion and the remainder is consumed by the peripheral circuit portion of the memory cell array portion. With the increase in the memory capacity, the ratio of the electric power consumed by the memory cell array portion becomes larger and larger, but the electric power consumed by the peripheral circuit portion does not increase much. Of the electric power consumed by the memory cell portion, most of the power consumption is caused by the bit line current flowing at the access time, i.e., at the time the read out or the write in of information is effected, and the electric current necessary for holding the information stored in the memory cells is very small. Therefore, it is essential to decrease the power consumption of the memory cell array portion, especially to decrease the bit line current, in order to decrease the power consumption of the memory device.
In order to decrease the bit line current, it is possible to divide each of the word lines into two half sections and to select only one of the half sections to which the selected memory cell is connected. In such a structure, another one of the half sections of the selected word line is not selected and, therefore, the total current flowing from the bit lines through the memory cell to the ground can be reduced approximately by one half. However, in such a memory device, the length of each of the bit lines is the same as that of the memory device of FIG. 1, and the stray capacitance of each of the bit lines becomes very large when the memory capacity is increased. Therefore, it is necessary to increase the charge current flowing from the transistors Q.sub.1 and Q.sub.2 to the bit lines, so that the power consumption becomes large when the memory capacity is increased.